This invention relates to an information processing device for use in carrying out vector calculation.
In U.S. Pat. No. 4,128,880 issued to R. Cray, Jr, a vector processing computer is disclosed which comprises a memory section, a plurality of vector registers coupled to the memory section, and a plurality of independent segmented functional units, such as adders and multipliers, operable in cooperation with the vector registers. A bulk of data signals are transferred from the memory section to the vector registers and are successively transferred in vector processing from one or more vector registers to one of the functional units to be processed and to be returned back to another one of the vector registers. Such vector processing is progressive in a chaining mode of operation under control of an instruction decoder or instruction interpreting unit coupled to a central processing unit and is therefore carried out at a high speed. For brevity of description, a combination of the vector registers and the functional units will be referred to as an instruction processing unit in the instant specification.
More specifically, a load instruction and a store instruction are delivered from the central processing unit to the instruction decoder on loading the vector registers with the data signals stored in the memory unit and on storing results of vector processing in the memory unit, respectively. In this event, the instruction decoder sends a memory enable signal or memory indication signal to the memory unit.
An arithmetic or operation instruction is also delivered from the central processing unit to the instruction decoder. Responsive to the operation instruction, the instruction decoder sends a unit enable signal or unit indication signal to the instruction processing unit. The instruction processing unit carries out arithmetic operation in accordance with the unit indication signal and the operation instruction. For convenience of description, the unit indication signal and the memory indication signal will be called first and second indication signals, respectively.
Let each load instruction be repeatedly issued from the central processing unit with the arithmetic instruction interposed between two adjacent ones of the repeated load instructions. In this case, processing is successively carried out in the order of a first one of the load instructions, the arithmetic instruction, and a second one of the load instructions. It is to be noted here that each load instruction is considerably time-consuming to be processed in comparison with the operation instruction because the memory unit should be accessed thereby. Usually, each of the load instructions is successively processed one after another. As a result, the second indication signal for the second load instruction must be produced after completion of a loading operation for the first load instruction. Accordingly, a long duration should be wasted between the second indication signals for two adjacent ones of the load instructions. This applies to the store instruction. From this fact, it is readily understood that the arithmetic calculation can not be carried out at a high speed when the memory unit is frequently accessed by the instruction decoder.